Abstract: The voltage-controlled delay line (VCDL) is one of the most sensitive subcircuits to single event (SE) in delay-locked loops (DLLs),which consists of a bias circuit and voltage-controlled delay cells. The sensitivity of VCDL in a DLL to single-event transient (SET) was analyzed based on double exponential current source and 3-D TCAD mixed-mode simulation. According to the difference in the severity of SET response and circuit structure,the bias circuit was hardened by analog redundancy,while a SET detection circuit was proposed for voltage-controlled delay cells. Simulations,making under the condition of 80 MeV·cm²/mg linear energy transfer (LET) values,1.2 V supply voltage and 1 GHz input reference clock,show the perturbed magnitude of biasing voltages,V_bn and V_bp,can be significantly reduced by 75% and 60%,respectively,completely eliminating missing pulses of output signals compared with the unhardened one. The proposed detection circuit can indicate SET response in voltage-controlled delay cells under different circumstances,improving the reliability of output signals in the DLL.