Abstract: In order to reduce the long latency and circuit complexity, a quaternary algorithm of AB+C and its implementation were presented based on systolic array structures in GF(2⁴). The systolic structure was arranged to employ a quaternary logic technique based on dynamic source-coupled logic to do arithmetic operations, to use current-mode signals to decrease the initial delay, transistors and wires. A simulation evaluation was carried out with a 0.18 μm CMOS technology. The results show that, compared with the corresponding binary CMOS implementations reported in references, the initial delay and the sum of transistors and wires in this design can be reduced about 54% and 5%. The parallel-in parallel-out systolic structure proposed is simplicity, modularity and scalability, being suitable for VLSI implementations. The scheme of combining multiple-valued circuits and corresponding algorithms based on multiple-valued logic (MVL) is expected to be a feasible alternative for super performance arithmetic units in GF (2^k).