Abstract: A high-speed hardware architecture was presented to implement modular inversion operations for the field of elliptic curve cryptograph (ECC) in the paper. Two hardware architectures based on Itoh-Tsujii algorithm (ITA), Least-Cock-Cycle-ITA (LCC-ITA) architecture and high-speed-ITA (HS-ITA) architecture, were built and implemented on Xilinx Virtex-5. In the architectures, power operations and multiplications were simplified into non-iterative logic to speed up modular inversion operations. The test results show that the operating frequencies of both architectures are higher than the work before. LCC-ITA architecture takes nine clock cycles to complete a modular inversion operation with the operating frequency 126.1 MHz over GF(2<sup<163</sup<), while HS-ITA architecture takes 20 cycles with the operating frequency 177.6 MHz over GF(2<sup<193</sup<).