Abstract: To reduce the testing time and decrease the testing overhead of hardware for SoC, a high-performance SoC test structure was presented. The structure could eliminate turnaround cycle existing in traditional bi-directional test bus by reusing memory controller as test interface, while it can avoid crucial path in test channel through establishing a pipelined test sequence. Aiming at both functional and structural test requirements, the on-chip bus reused as TAM without the destructive modification could shorten the waiting cycles of test access. To balance the bandwidth between test paths and scan chains, a test wrapper independent of target core was integrated. Test results show that the approach shortens the testing time by 68%, and reduces the area overhead by 36.1%, which considerably mitigates the effects on the performance of the original chip.