A Design of a 2 bit/cycle SAR ADC Design with Noise Shaping

An 8-bit 100 MS/s successive approximation register analog-to-digital converter (SAR ADC) with 2 bit/cycle structure was designed for 180 nm CMOS process. Two DAC capacitor arrays, SIG_DAC and REF_DAC, were used to implement 2 bit/cycle quantization. Upper plate sampling technique was adopted to greatly reduce the number of capacitors in SIG_DAC. Split-capacitor structure and optimized asynchronous SAR logic were arranged to improve the conversion speed of ADC. A noise shaping technique was applied to effectively improve the signal-to-noise-distortion ratio (SNDR) of the ADC at oversampling. The results show that without noise shaping, the proposed ADC can get 46.22 dB SNDR at 100 MS/s rate with 1.8 V supply voltage. Through noise shaping, the simulation results show the SNDR is increased by 11.27 dB to 57.49 dB at an over-sampling rate 10, which means the ENOB of ADC is increased by 1.88 bit and reaches 9.26 bit.