Design and Implementation of a Runtime-Configurable Two-Dimensional CFAR Processor

A hardware architecture of runtime-configurable two-dimensional constant false alarm rate (CFAR) processor was proposed based on FPGA to improve the algorithm speed for multi-scenario. This processor was designed to implement four pipeline architecture operations, cell averaging (CA), greatest of (GO), smallest of (SO) and ordered statistics (OS), for two-dimensional rectangular window (2D-RW) detectors. Also, controlling correlative parameters, this processor could make the reference window size, guard window size and detector type configurable. Test results show that, for 256×512 points data, the computation time of each detector in the processor is less than 3ms, and the relative error of detection threshold is no more than 0.1%, validating its better detection ability for two-dimensional radar data.