Design of Low-Power Successive Approximation Register Analog-to-Digital Convertor Based on a Time-Domain Comparator

In this paper, a 10 bit low power successive approximation register analog-to-digital converter (SAR ADC) was presented based on a time-domain comparator in 90 nm CMOS. Compared with conventional dynamic comparator, the time-domain comparator was arranged with differential multi-stage voltage controlled delay lines to convert voltage to time signal, and the time difference was sensed by a phase detector to reduce influence of common-mode various and static power consumption. And a partial monotonic switching strategy was employed to convert voltage in capacitor array, cutting down total capacitance and power consumption. Simulation results show that, with 1 V power supply, 308 kS/s at Nyquist sampling rate and 0.9 V signal scope, the ENOB can achieve 9.45 bit with 13.48 μW power consumption.