Design of quaternary logic circuits based on source-coupled logic

In order to improve the performance of arithmetic very large-scale integration (VLSI) system, a novel structure of quaternary logic gates is proposed based on multiple-valued current mode (MVCM) by using dynamic source-coupled logic (SCL). Its key components, the comparator and the output generator are both based on differential-pair circuit (DPC), and the latter is constructed by using the structure of DPC trees. The pre-charge evaluates logic style makes a steady current flow cut off, thereby greatly saving the power dissipation. The combination of multiple-valued source-coupled logic and differential-pair circuit makes it lower power consumption and more compact. The performance is evaluated by HSPICE simulation with 0.18. μ m CMOS technology. The power dissipation, transistor numbers and delay are superior to corresponding binary CMOS implementation. Multiple-valued logic will be the potential solution for the high performance arithmetic VLSI system in the future.